Typically in pattern defect inspection procedures, a one-dimensional (1D) or linear image sensor is used as the image detection means for picking up the image of an object to be tested. FIG. 4 is a diagram showing an arrangement of such image sensor 8, and FIG. 5 is a plan view of an inspection area of the object being tested, for indicating the area that is image-detectable by a single time of scanning. Scan the object under test in a direction at right angles to the layout direction of picture elements or “pixels” 81 of the image sensor 8, thereby acquiring a two-dimensional (2D) image. The length of the direction along which the pixels 81 are queued is called the “height” of the image sensor 8. In addition, in case the object under test is assumed to be a semiconductor wafer having a plurality of semiconductor chips being presently fabricated, the length of a single chip in the same direction as the height of image sensor 8 is called the chip height. Generally the chip height is larger than the height of image sensor 8, so it is merely possible to detect only an image of part of the chip through one-time scanning of the image sensor 8. The significance of this chip's partial image is determinable depending upon the height of the image sensor 8 that performs detection and the imaging magnification of an image focussing optical system for projecting the chip image onto this image sensor 8. This height is called the effective image pickup height of the image sensor 8. In a combination of a currently used image sensor and its associated image focusing optical system, the effective image pickup height is less than the chip height. Accordingly, in order to inspect an overall chip surface, a method is employed for scanning it while offsetting in the height direction for multiple times.
FIG. 6 is a plan view diagram showing a sensor scan locus 101 in case a plurality of chips 21 that are formed on a wafer are scanned by an image sensor for several times. Usually in the pattern defect inspection apparatus, the image sensor is fixed while using a stage to move the wafer under test. Firstly, let the test object move in the X direction; then, acquire an image. Information per pixel of one chip 21 is stored in a memory in the order of scanning. After having completed the image detection in a one-time scan cycle, let the test object move in the Y direction by a distance corresponding to the effective image pickup height of the image sensor. The stage is driven to shift in position as indicated by broken line in FIG. 6 so that the scan direction becomes reversed. This will be repeated to thereby achieve sequential image detection.
While inspection of the chip 21 is performed by image comparison of the same patterns, the image of a test area “c” is used as a reference image in the case of testing an area “b.” However, when testing an area “a” that is the forehand chip of each row to be scanned, it is impossible to perform any intended inspection due to the absence of a reference image in an area immediately preceding the same pattern. This would result in generation of noninspectable areas or regions in the outer periphery of the wafer. For this reason, non-inspectable chips would take place in those in the wafer outer periphery.
In prior known pattern defect inspecting apparatus, there is the one that solved the above-noted problem by modifying the scan method (for example, see JP-A-11-160247). FIG. 7 is a plan view showing the scanning locus of an image sensor in a similar way to FIG. 6. In this case, the effective image pickup height of the image sensor is one-third (⅓) of the chip height. Assume that scanning is done while dividing the test area into three strip-like regions. Although the scanning of the first row in the X direction is the same as that shown in FIG. 6, the second row is scanned while causing an object under test to move by a distance corresponding to the height of one chip in the Y direction. This will be repeated for execution of comparative inspection of the images of identical patterns each having its region equal in size to ⅓ of a chip. Upon completion of the last row, as indicated by dotted line in FIG. 6, the image of the same pattern in the next ⅓ regions of the chip is subjected to comparison inspection. After having finished the first chip, comparison inspection is done for the image of the same pattern in the remaining ⅓ region of the chip.
In the case of testing of an area “b” which is immediately after a fold-back or a halfway point, the pixel information of the area “c” for use as a reference image is read out in an order reverse to the order at the time of data storage, whereby the comparison inspection is executable while letting the area b and area c be the same pattern image. Optionally, the image of another area of the same pattern may be prestored as the reference image of the area a upon startup of the inspection. Whereby, it is possible to perform the inspection of the area a also.
However, in any one of the pattern defect inspection apparatus for performing inspection based on the scan locus shown in FIG. 6 and the pattern defect inspection apparatus for performing inspection relying upon the scan locus shown in FIG. 7, comparative inspection of the detection image of a chip is performed by comparing it to the reference image of its immediately preceding chip with the same pattern. Using the image of such immediately preceding chip in this way raises problems which follow.
An object under test for use as the object being subjected to pattern defect inspection is such that a pattern is typically formed of a material that is transparent with respect to the wavelength of visible light, such as a photo-resist or a dielectric film made of SiO2 or the like. In this case, even if a thin film is transparent relative to the wavelength of light being used in the defect inspection apparatus, it exhibits certain reflectivity which is determinable by such the light wavelength and the refractivity of a material making up the pattern plus a film thickness. This makes it possible for the defect inspection apparatus to detect its presence as a light-and-shade image. FIG. 1 shows an exemplary wafer having a pattern of thin film formed thereon, which is made of a material transparent to the wavelength of light being used in the defect inspection apparatus. Generally in such the wafer, the thickness of the thin film pattern is not perfectly flat on an entire wafer surface but slightly different depending on locations; however, a certain degree of film thickness error is made acceptable because such error does not affect the manufacture of semiconductor chips. Unfortunately, a difference in film thickness occurring depending on locations can create a likewise difference in reflectivity of the pattern, resulting in occurrence of an appreciable difference in brightness or luminance of an image to be detected. This phenomenon is called the color shading irregularity. For example, suppose that a neighboring chip “n” and its immediately preceding chip n−1 of FIG. 1 are such that the same shaped patterns “p” included therein are different in film thickness from each other, resulting in occurrence of color shading. In this case, if the comparison inspection is carried out while letting the chip n be a detection image and also regarding the chip n−1 as a reference image, then the pattern p must be erroneously detected as a defect. This occurs because the resultant image is different in light-and-shape property even though the pattern p is the same in shape between these two images and no defects are present therein. Such the false defect information raises difficulties in distinction from a true defect and thus is a serious problem relating to the reliability of the inspection apparatus.
Prior known approaches to avoiding the above-noted false defect information include two methods which follow:
(1) increasing the threshold value so that the color shading irregularity is insensitive to test results during inspection while comparing a detection image to reference image, wherein the threshold value becomes a criterion for judgment of which degree of difference is regarded as a dominant difference; and
(2) correcting or amending the influenceability of color shading irregularity occurring between the detection image and reference image and then performing comparison inspection after removal of the color shading.
The advantage of the method (1) does not come without accompanying the following penalties: the inspection apparatus decreases in detection sensitivity; and, its detection ability or “detectability” for true defects decreases simultaneously. Regarding the method (2), this is a method such as shown in JP-A-2000-97869 for example. Estimation of the degree of the color shading at a chip position of the detection image from the reference image of its immediately preceding chip is equivalent in principle to estimating by interpolation unknown information in the future from known information in the past. In addition, utilizable information items are as less as two images i.e., a single plane of detection image and a reference image plane. Thus, this method is disadvantageously limited in effects for enabling correction and removal of the color shading influenceability.
A pattern inspection apparatus is disclosed in JP-A-10-74812, which apparatus detects an image signal from a repeated pattern to be tested, and generates from this detected image signal a statistical image signal of the repeated pattern being tested, and then uses this generated statistical image signal as a reference image signal to compare it to the above-noted detected image signal while applying thereto position alignment, thereby extracting a defect or a defect candidate that is present in the pattern under test.
JP-A-3-286383 discloses therein a surface defect inspecting apparatus for detecting defects based on a pattern difference. This apparatus comprises means for sequentially accepting first patterns, pattern generator means for calculating an average value of the first patterns accepted by the accepting means to thereby generate a second pattern, and means for comparing the second pattern thus generated to a newly accepted first pattern and for detecting a pattern difference, if any.
JP-A-5-218160 discloses a semiconductor chip appearance inspection apparatus which includes a first image memory that sequentially temporarily stores dark-and-light grayscale information of a plurality of semiconductor chips obtained by dicing a single piece of wafer, a second image memory for storing reference grayscale information used for execution of comparative judgment by comparison with the grayscale information of the first image memory, a defect-free product detector unit for comparing the grayscale information of the first image memory to that of the second image memory to thereby detect non-defective semiconductor chip products, and an image averaging processor unit for performing, when the defect-free product detector unit judges a chip as a good product, computation of the grayscale information of the first and second image memories, for rewriting the grayscale information of the second image memory based on the computation result, and for allowing the rewritten information to become a new reference grayscale information.